1. Field of the Invention
The present invention relates to a novel method of producing flexible interconnections for integrated circuits, and, in particular, although not limited thereto, to the provision of forming flexible or compliant interconnections in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology. In particular, the integrated circuit chip or the plurality of chips, which are mounted on a carrier, is or are connected to a next level package or a circuit board, and wherein the next level package may be constituted of a ceramic or an organic composite depending upon particular intended applications.
Basically, in the formation of integrated circuits employing organic chip carriers, the provision of a flexible or compliant interconnection assumes great importance in maintaining the operative integrity of the integrated circuits, due to the differences, which are frequently encountered in the mismatches in the thermal coefficients of expansion (CTE), which are present between the organic chip carrier and the chip or chips, or a silicon carrier (Si-carrier), which is bonded thereto.
In essence, when the applicable chip or the Si-carrier is, or chips or carriers, are of a large size or sizes, the mismatch between the respective CTEs is further increased, inasmuch as the flexible interconnection size must be specifically designed to take cognizance of the differences in the absolute physical movement or displacement between the respective components as a function of the displacement or distance which is measured from a so-called neutral point of the overall semiconductor structure.
Generally, the differences or mismatches which may be present in the coefficients of thermal expansions between the components create problems in the fatigue life of the interconnection in response to an increase in the difference or mismatch between the CTEs of the substrate and the chip or chips. In the prior art, and in current state of the technology, cognizance has been given to such differences or CTE mismatches in the x and y-directions or planes of the integrated circuit structure. However, although the movements in the x and y plane to which considerations have been given in improvising solutions in the formation of the compliant or flexible connections between a chip and carrier, and have been extensively treated in the prior art, and have also been addressed in applicants' co-pending U.S. patent application Ser. No. 10/686,640, filed on Oct. 17, 2003, the disclosure of which is incorporated in its entirety herein by reference, that application being commonly assigned to the assignee of the present application.
In order to provide a compliant or essentially flexible interconnection, which will take cognizance of the CTE mismatches which are encountered between the chip or chips and the substrate or carrier components, utilization has been implemented of methods of laser assisted chemical vapor deposition (LCVD) of the conductors which form the electrical interconnections. Thus, for instance, in order to form the interconnections, any metal which is suitable for that purpose can be deposited by means of laser assisted chemical vapor deposition (LCVD), wherein such metal forming the interconnection may be suitably constituted of, but not limited to, tungsten, molybdenum, tantalum and platinum, although tungsten is preferably the most widely employed of these types of metals.
For example, pertaining to the basic concept of chemical vapor deposition (CVD), a solid material is deposited from gaseous reactants through chemical reactions onto or in the vicinity of a heated surface. The resulting properties of the deposited material can be readily controlled by appropriate regulation of the process conditions, and which normally entails a multi-step process in order to form the interconnections. In implementing the LCVD, a laser is employed in order to thermally or photochemically activate the CVD process, whereby laser frequencies are selected such that the gaseous reactants do not absorb the radiation, and a focused laser may be utilized as a localized heat source. The laser may be either a continuous wave laser or, alternatively, a pulsed laser, wherein the use of such LCVD processes, including the thermally activated CVD process, is known in the current state of the technology. The CVD techniques may be employed to deposit various solid materials, such as metals, alloys and non-metals and compounds comprising carbides, nitrides and oxides, whereby deposition of the material may be in the form of thin films, fibers, powders, rods or other three-dimensional structures.
For the purpose of testing integrated circuit chips in wafer, singulated, carrier, or package form, it is important for a probing substrate to have a compliant or flexible probe tip or interconnect, due to non-planarity of surface pads or solder bumps that are present on the surface of the wafer, chip, carrier, or package. Furthermore, it is desirable to have a probe tip surface to be mechanically and chemically durable and physically abrasive such that upon physical contact with the device under test (i.e., wafer, chip, carrier, or package), any existing surface oxides and residues that may have formed on the surface of a pad or a solder bump are effectively removed to assure a low resistance electrical contact during testing.
Heretofore, in the current state of the technology, either no consideration or only a limited degree of consideration has been given to the forming of flexible interconnects in integrated circuit structures which take cognizance of compliance in the z-direction, in addition to compliance in the x and y planes.
For instance, especially in the case of an organic chip carrier, is a matter of extreme importance, that in connection with the use of a flexible interconnection there must be accounted for differences or mismatches in the thermal coefficients of expansion (CTEs) between the interconnection and the chip or the Si-carrier which is bonded thereto.
As indicated in FIG. 7 of the drawings, which sets forth fatigue life-cycles versus coefficients of thermal expansion of the substrate, there is a clear correlation of the interrelationship in the fatigue life-cycle with regard to the differences which are evident between the substrate and chip coefficients of thermal expansion.
Furthermore, the stress and strain, which is created by the interconnection due to the physical dimensions of the chip or carrier and the height of the interconnection, have an important bearing on the provision of a compliant or flexible interconnection in the z-direction. Although ceramic chip carriers attractive from the standpoint of their thermal characteristics, they are expensive to produce and in order to reduce manufacturing costs, extensive considerations are being given to the use of chip carriers, which are constituted of polymeric materials. Nevertheless, the difference in the coefficients of thermal expansion (CTEs) between the chip and the carrier is evident to a degree so as to cause significant problems with regard to the integrity and service life expectancy of standard C4 connections.
2. Discussion of the Prior Art
For example, in effecting formation of a compliant connection between a chip and carrier allowing for movements in the x- and y-plane, which take into consideration compensating for CTE differences or mismatches, prior art publications, such as Patel, et al., U.S. Pat. No. 6,528,349 B1; Takiar, et al., U.S. Pat. No. 6,521,970 B1; Khandros, et al., U.S. Pat. No. 6,372,527 B1; Fjelstad, et al., U.S. Pat. No. 6,211,572 B1; DiStefano, et al., U.S. Pat. No. 6,104,087; and Bezuk, et al., U.S. Pat. No. 4,845,542, each disclose diverse methods and structures directed to the build up of compliant or flexible interconnections and are primarily concerned with complicated multi-step and consequently, expensive processing procedures in the manufacture of integrated circuits or the like structures.